The EDT PCIe8g3 A5-40G supports PCI Express – PCIe, Gen3 – x8 and has a 40G QSFP+ and 40 GbE or OTU3. The board is available as half-height or full-height. The port links to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 1 – 808 MHz programmable reference clock. The UI FPGA is a Altera Arria V GZ (E3, E5, or E7) with access to one DDR3 DRAM, 2 GB 64-bit, that is also a buffer. The PCIe FPGA provides up to 8 independent DMA channels via EDT FPGA configuration files. An optional Lemo supports 1 pps or IRIG-B) time codes, with either DB9 or BNC. Configuration files support 40 GbE at PCS and PMA, and OTU3 – raw, framed, framed and descrambled.