The EDT PCIe8g3 A5-10G supports PCI Express – PCIe, Gen3 – x8 and has two 10G SFP+ and 1 – 10 GbE or OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. This low-profile board is available as a half-height or full-height backpanel. The port links to the SERDES user-interface for serialization and deserialization, and clock recovery and its own 1 – 808 MHz programmable reference clock. The UI FPGA is a Altera Arria V GZ (E3, E5, or E7) with access to one DDR3 DRAM, 2 GB 64-bit, that is also a buffer. The PCIe FPGA provides up to 8 independent DMA channels via EDT FPGA configuration files. An optional Lemo supports 1 pps or IRIG-B) time codes, with either DB9 or BNC. Configuration files support 1 and 10 GbE at PCS and PMA, and OC3/12/48/192 and OTU1/2/2e/2f – raw, framed, framed and descrambled.