The EDT PCIe8g3 KU-10G supports PCI Express – PCIe, Gen3 – x8 and has a 40G QSFP+ and two 10G SFP/+ ports. Supported protocols are 1/10GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f. Each port links to the SERDES user-interface for serialization and deserialization, and clock recovery. Each port has its own 10 – 210 MHz programmable reference clock. The UI FPGA is a Xilinx Kintex Ultrascale (U035, 060, 085, or 115) with access to two independent DDR3 DRAMs, each 2 GB 64-bit, that are also buffers. At power on, it configures from flash and can be repeatedly reconfigured without power cycling. Up to five images are available. The PCIe FPGA provides up to 16 independent DMA channels via EDT FPGA configuration files. An optional Lemo supports 1 pps or IRIG-B) time codes, with user-configurable output and two options for cables. Configuration files support 1 GbE and 10 GbE at the PHY layer; OC3/12/48/192 and OTU1/2/2e/2f – raw, framed, framed and descrambled); and demultiplexing. Custom files available.