DIME-C

ANSI-C to VHDL Compiler
DIME-C is the Nallatech C-to-VHDL compiler; it can be used within DIMEtalk V3 as part of the HPC Toolkit or within the Nallatech Accelerator Layer (NAL) when designing for FSB (Intel Front Side Bus). Alternatively, DIME-C can generate VHDL that could be reused in any VHDL designs for Virtex 4 and 5 Xilinx FPGAs.



Overview

DIME-C is the Nallatech C-to-VHDL compiler; it can be used within DIMEtalk V3 as part of the HPC Toolkit or within the Nallatech Accelerator Layer (NAL) when designing for FSB (Intel Front Side Bus). Alternatively, DIME-C can generate VHDL that could be reused in any VHDL designs for Virtex 4 and 5 Xilinx FPGAs.
A DIME-C project will generate a top level VHDL entity that will have to be instantiated in the hardware system design or imported in a DIMEtalk project.
The DIME-C compiler should be used to design and optimise algorithms. Although DIME-C supports ANSI-C it is important to note that in order to obtain a fast implementation of a design some rewriting of the code might be needed; the DIME-C documentation describes good practice techniques.

Key Features

* Supports a subset of the ANSI-C grammar: including structures, arrays… (no pointers)
* Generates synthesisable VHDL for Xilinx Virtex 4 and 5 FPGAs (can also be simulated)
* Supports single and double precision floating point (IEEE754 32 and 64-bit)
* Automatically optimised code: pipelined and parallelised when possible
* Shared resources between parallel processes
* Non cycle accurate implementation to reach a higher design frequency
* Algorithm Visualisation Tool
* Use of Virtex 4 and 5 Xilinx FPGA dedicated hardware: DSP48 slices, RAM blocks
* Interface to Nallatech DIMEtalk V3
* Library interface for user blocks
* Math library (similar to math.h)
* Optimised libraries for memory access (Nallatech hardware SRAM and SDRAM banks)
* GUI based environment
* Command line arguments

Benefits

High-level language compiler
No VHDL required when programming an FPGA when DIME-C is used with DIMEtalk V3. DIME-C supports single and double precision floating point operations and a single precision floating point math library.

Automatically optimised designs
When possible the source code will be pipelined and parallelised to provide an optimised implementation of the algorithm. Furthermore, DIME-C uses in priority optimised IP and dedicated hardware resources of Virtex 4 and 5 Xilinx FPGAs.

Development Environment
DIME-C can be used in a GUI version under Windows XP and command line version under Windows XP and Linux (Red Hat based platforms).

Optimised interfacing to Nallatech Hardware
When the developed algorithm requires access to Nallatech DDR-II SRAM and SDRAMs, DIME-C provides an optimised interface to make the most of the available bandwidth.

Many examples, tutorials and documentations

Environment

A GUI is available for Windows XP and a set of command line arguments can be used to compile projects on Windows XP and Linux systems (Red Hat based platforms) consequently a DIME-C project can be compiled from a script or a Makefile.
The DIME-C code can be recompiled with a standard C compiler (like GCC) and tested within the original user software to validate any alteration made to the algorithm in DIME-C. A VHDL test-bench is generated when compiling a project for the user to check the functionalities of their design (not compulsory in the design process).
DIME-C automatically pipelines and parallelises the code when it is possible and will inform the user of the pipeline status of each parts of their algorithm. In parallel processes resources will be shared when possible.
Xilinx DSP48 blocks are used in priority before using logic-only IP cores and 2 independent accesses to internal BRAMs per clocks cycle are possible: 2 reads or writes, or 1 read and a write.
DIME-C creates designs that will usually compile for runtime frequencies between 100 MHz and 200 MHz.