The Nallatech 520 is a PCIe accelerator board built using the Intel Stratix 10 FPGA with four 100G QSFP Ethernet ports and a PCIe Gen3 x16 host interface. With fast, independent optical I/O, establish dense, directly coupled FPGA clusters.
This scalable compute node is intended for intensive computing and latency-critical applications from Network Analysis to Machine Learning. With unique single precision floating point speed to 10 Tflops, each FPGA has four banks of DDR4 external memory.
With four optical network ports, FPGA-to-FPGA can be scaled without funneling though PCIe. The serial IO array protocols operate at up to 100G.