Gidel FPGA IP Core for Real-time JPEG Compression | Compact Silicon | Low Latency

The Gidel JPEG Compression FPGA IP Core encodes JPEG at high-performance. The compression IP is fast processing, low latency, and compact silicon utilization. The IP can compress high-performance camera image streams on a small FPGA device, or alternatively, multiple instances can run on a single larger FPGA device.

The IP includes a host interface and an API suite for software control.

The JPEG IP’s input stream is in YCbCr format with an optional converter from RGB, monochrome, etc. The degree of compression can be adusted to allow a  tradeoff between storage size and image quality.

Color subsampling can be encoded in 4:2:2, 4:4:4 or 4:2:0 formats. The following table shows a compression performance example using 4:2:2 encoding at 540 MPixels. The latency for this example is 130 uS.

Compression Performance Example

FPGA Arria 10 (slowest device)
Throughput 1,080 Mega components/s
Line size 8K pixels/line
Bit / Component 8
Area (ALMs) 5000
M20K 151
DSP blocks 64

The IP is supported by Gidel’s comprehensive ecosystem of optimized vision system solutions that may include image processing, vision algorithms and a concurrent recording system. The recording system may also be complemented by Gidel’s CamSim playback system.

The IP is also supported by optional image binning decompression software. This feature can be used for displaying videos from multiple cameras during a recording session, or for quickly reviewing a large image set.

Gidel JPEG Compression IP Core with more then 1 Giga components/s compression performance and high performance sensor image streams.
Gidel JPEG Compression IP Core: compression performance beyond 1 Giga components/s.
Gidel JPEG Compression IP Core implementation using InfiiVision, compression and custom image processing.
Gidel JPEG Compression IP Core: with InfiiVision, compression and custom image processing implementation.

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