EDT VisionLink CLS is a new generation of a camera link that designed to facilitate development and testing of imaging systems, cameras, and software by using actual or generated images. Internal counters can be used as alternative source of image data. Images are transmitted via Direct Memory Access (DMA) from the host computer with data rates of up to 850 MB/s, 85 MHz, 10-tap, and 8-bit. Pixel clock rate is from 20 to 85 MHz. The VisionLink CLS is featured with FIFO data memory and supports several lines of data. Common configurations for the camera link simulator include base, dual base, medium, full, and extended full modes.
The Camera Link simulator is a half-length / full-height PCI Express Gen3 board with 8 lanes. The simulator has 2x SDR26 camera link connectors for data and control needs. SDR-to-SDR or SDR-to-MDR cabling options are available. Windows and Linux software is included, other software – on request.