The EDT PCI CDa board provides one high-speed 16-bit parallel channel or an optional 16 synchronous serial channels between an external device and a PCI local bus computer (or optional 16-channel* synchronous serial interface). The device interface uses LVDS- or RS422-compatible driver/receivers connected to a field-programmable gate array (FPGA).
The PCI CDa uses direct memory access (DMA) and asynchronous I/O to achieve transfer rates to or from memory of up to 210 megabytes per second (observed). The hardware protocol is synchronous; that is, all data and control signals are sampled with a clock transmitted along with the data and control signals. This clock may be generated by the DMA interface or the user device or both. All signals are differential using LVDS (or optional RS422) specifications.
The PCI CDa includes a versatile, straightforward protocol but optional customer-specific protocols may be developed.
* For 16-channel capability, the CDa must have an optional Xilinx XC2S600e installed and use the ssd16io bit file.
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