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Sky Blue Microsystems GmbH of Munich is an international distributor for Gidel.

FPGA Board Level Solutions | Vision Systems and Imaging | Frame Grabbers | Advanced FPGA Development Tools | Support for HLS, Open Vino AI and ML libraries, and MVTEC

Gidel has 25 years experience developing high-end FPGA systems as products for sale or as integration projects for customers using a combination of industry standard tools such as OpenCl, and internal advanced development tools, which are also available to end-customers.

Gidel products, tools, and expertise are used in applications including security, DNA research, machine learning, imaging and vision systems, augmented and virtual reality, deep learning, and reconfigurable interconnect frameworks for HPC clusters.

An intelligent FPGA solution for high performance FPGA acceleration from Gidel requires speed, compute efficiency, and best use of memory capacity and bandwidth.

Gidel has the knowledge, experience, and has developed extremely stable tools based on the latest technology to reduce development time and effort and to ensure long product life cycles.

Sky Blue Microsystems GmbH of Munich, Germany, provides advanced electronics products for science and industry, and is an international distributor for Gidel. Sky Blue also operates through its wholly owned subsidiary, Zerif Technologies Ltd, of Nottingham in Great Britain.

Gidel’s smart FPGA platforms combine high-end compute performance, system flexibility, powerful development tools and provide diverse solutions for diverse markets.
Gidel’s smart FPGA platforms combine high-end compute performance, system flexibility, and powerful development tools.

TotalHistory IP Core for Signal Tracing

Gidel’s Total History IP Core is an innovative signal tracing tool for FPGA prototyping enabling virtually unlimited signal trace depth, and massive and flexible probing of real system performance. TotalHistory uses the unused on-board memory and memory bandwidth of the FPGA boards, thus requires no additional resources.

GiDEL’s novel TotalHistory IP opens the way to unprecedented design visibility. TotalHistory is based on a unique design-embedded IP core. Probes are inserted at any design point of interest to capture signals at full operating speed; signal trace is stored in the on-board memory or on peripheral SODIMMs at practically unlimited depth (up to 8.5 GB/FPGA) enabling virtually infinite signal tracing regression to accurately detect, reproduce, and isolate system bugs. Real-time signals are channeled to the host allowing user application processing to generate complex triggering schemes to detect bugs and to capture vital internal signal states. Once a trigger is issued, virtually infinite signal trace history can be retroactively analyzed by the host application, or by a simulator via the PCI/e bridge, or via Gigabit Ethernet (in the case of a PROC_SoCTM system). TotalHistory can support as much as 100,000 fully configurable probes per FPGA permitting comprehensive signal visibility.

InfiniVision for camera arrays

Gidel’s InfiniVision technology allows development of Augmented and Virtual Reality products to utilise high quality image content from a large camera arrays to generate 360 degree panoramas for the latest immersive entertainment and sports experiences.

Reconfigurable Interconnect Frameworks for HPC clusters

Gidel’s low-latency, full duplex direct FPGA connectivity technology allows customers to build Reconfigurable Interconnect Frameworks for HPC clusters with no CPU overhead. 3D and 12D Torus and 6D and 24D Hypercube topologies can be optimized to become the HPC infrastructure required for compute-intensive workloads.

Gidel’s “Developer Suite”

The Gidel Developer’s Suite is based on 25 years of continuous improvement. Developer’s Suite gives you unmatched development productivity. The Gidel Developer’s Suite consists of:

Proc Developer’s Kit

Proc Developer’s Kit (ProcDev Kit), as an alternative to existing FPGA design methodologies. It is oriented towards implementing your algorithms in a user friendly and efficient manner.

High Level Synthesis Application Support Package

HLS Application Support Package (I++) allows you to use Intel’s High Level Synthesis (HLS) tool, which generates Register Transfer Level (RTL) from C++ input. The output is optimized for FPGAs.

Intel Open Vino AI and ML libraries

Gidel supports Intel’s Open Vino Artificial Intelligence and Machine Learning libraries.

Halcom MVTec Libraries and Utilities

Gidel supports Halcom’s MVTec comprehensive standard software for machine vision applications.

OpenCL BSPs

Gidel provides OpenCL Board Support Packages (BSPs) for FPGA compute accelerating.

For more information, please call +49 (0) 89 – 780297 0, or email us at info@skyblue.de, or fill out this form: