EDT 3P Mezz – 10 Gb, 1 GbE, or up to OC48 (STM16) interface – Sky Blue Microsystems GmbH

EDT 3P Mezzanine Board with Xilinx Virtex 6 and 3 SFP / SFP+ channels

This solution is superseded by the EDT PCIe8g3 KU series products for 4P functionality. However, this mezz should still available for 3P or legacy applications.

The EDT 3P is a three-port mezzanine board that mounts on a PCIe main board to provide three independent channels, each supporting either SFP or SFP+. Channel 0 supports up to 10 GbE (optical), while channels 1 and 2 support 1 GbE or OC3/12/48 (STM1/4/16) each, electrical or optical. The user-configurable FPGA (Xilinx Virtex 6 XC6VLX240T, LX365T, or SX315T) can access three independent 512 MB blocks of DDR2 DRAM, which can be used as data buffers. Two of these can be combined to create a 1 GB memory block. Each channel links to a SERDES via a specialized LIU or, optionally, via a multi-gigabit transceiver (MGT) in the FPGA. For channel 0, the LIU is 10G; for channels 1 and 2, it is SONET/ SDH. Each channel has its own reference 10 to 210 MHz programmable clock, and a time code input of 1 pps or IRIG-B. Configuration files support 1 GbE and 10 GbE data at the PHY layer (raw, framed, and framed and descrambled), SONET / SDH (raw, framed, framed and descrambled, header, and payload data), and demultiplexing to VC-4C payloads. Custom configuration files are available. DMA is on the main board supplies DMA, plus more memory and FPGA.

Product Data

3P Mezzanine with Xilinx Virtex 6 for PCIe main board equipped with 3 channels 10Gb, 1GbE, or OC48 (STM16) and 3 independent DDR2 DRAM blocks  – Engineering Design Team, Inc.
EDT 3P Mezzanine Board with Xilinx Virtex 6: 3 channels supporting 10Gb, 1GbE, or OC48 (STM16).