The Gidel Proc Developer’s Kit (ProcDev Kit) is an easy to use FPGA design tool. It optimises on-board memory and host communication in support of your algorithm implementation on the FPGA.
The Developer’s kit includes the ProcWizard application, an API, Gidel IPs, examples, and HDL and software libraries.
The Gidel ProcWizard™ is a hardware–software integration tool that simplifies FPGA project development. ProcWizard enables rapid design of applications intended to run on Gidel FPGA boards.
The design is automatically translated into HDL and C++ code. The generated HDL and C++ code communicate over the PCIe bus for easy integration of the hardware and software.
ProcWizard can also be used to test and debug designs on your PC. In Debug Mode, you can access the Gidel “Proc” FPGA board via a structural inspector, either manually or by using macros and scripts.
Hardware and software designers can cooperate using the same information and project definitions. Working in parallel in the Gidel ProcWizard shared environment, development time is reduced, product reliability is increased, and maintainability is improved.
ProcWizard’s main features include:
The Gidel “ProcDev” Developer’s kit includes a set of IPs for simplifying and enhancing development tasks.
The Gidel MultiPort IP is a memory controller that optimizes on-board memory according to application data flow needs. This controller enables parallel access from up to 16 independent ports per memory bank. Each port may belong to a separate logical memory. All ports are connected to the same memory domain and can be accessed independently or simultaneously, with individual clock domains and data widths.
The MegaFIFO allows simple and convenient data transfer between the FPGA board memory banks and the FPGA logic and or the PC host.
The MegaDelay IP allows high-bandwidth delays to optimize streaming applications. This IP may significantly reduce memory access requirements, when combined with the FPGA’s internal memory and logic.
HLS Application Support Package (I++) enables the use of Intel’s High Level Synthesis (HLS) tool, which takes C++ as input and generates FPGA-optimized Register Transfer Level (RTL). The significant code reduction reduces the RTL verification time.
The Gidel JPEG Compression FPGA IP Core encodes JPEG at high-performance. The compression IP is fast processing, low latency, and compact silicon utilization. The IP can compress high-performance camera image streams on a small FPGA device, or alternatively, multiple instances can run on a single larger FPGA device.More…