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Gidel ProcVision Complete Development Suite for Industrial Machine Vision Systems

CertifEye Templates | Gidel Imaging Library (GIL) | ProcFG Frame Grabber application | Infinivision multi-camera grabber | CamSim camera simulator | ProcDev Development Kit | TotalHistory signal tracing | Utilities

The Gidel ProcVision Developer’s Suite includes CertifEye Templates for instant debugging and validation of FPGA image processing IP(s) and your ISP pipeline, FPGA’s Gidel Imaging Library (GIL), ProcFG frame grabber application supporting GenICam, ProcFG templates for instant porting of CertifEye-developed ISP to target frame grabber and acceleration board, InfiniVision multi camera frame grabber including compression and recording subsystems, CamSim real-time playback and ISP simulator, ProcDev Kit to fully tailor your frame grabber and ISP to your application needs, TotalHistory to access wide and signal tracing depth, and many utilities.

Gidel CertifEye Templates

The Gidel CertifEye templates allow instant debugging and validation of FPGA image processing IPs and ISP pipeline.

GIL Gidel FPGA Imaging Library

This imaging library is optimized, easy to use, and can be combined with your ISP.

Gidel ProcFG frame grabber application with GenICam support

Gidel ProcFG is a frame grabber application that supports GenICam and enables instant porting of CertifEye-developed ISP to target grabber and acceleration boards. See full description below.

Gidel Infinivision multi-camera frame grabber and recorder

Gidel Infinivision is a frame grabber for multiple cameras or sensors that supports compression and recording subsystems. See full description below.

Gidel CamSim camera simulator

The Gidel CamSim application is a real-time playback and ISP simulation solution. See full description under “Camera Simulators”.

Gidel ProcDev FPGA development kit

The Gidel ProcDev FPGA dev kit is a comprehensive FPGA fast development environment for reliable and stable FPGA applications that are easy to debug and maintain. See “FPGA Boards”.

Gidel TotalHistory signal tracing

With Gidel TotalHistory, you can access wide and virtually unlimited signal tracing depth.

Gidel Utilities

The Gidel utilities include new designs and FPGA scans, for example.

Product Data

Gidel’s flow diagram showing ProcVision Development Suite develops User image processing IP design on FPGA.
Flow diagram: User image processing (IP) design on FPGA.

For more information, please call +49 (0) 89 – 780297 0, or email us at info@skyblue.de, or fill out this form: